Daniel Avella Ordonez
Computer Systems Engineer
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16-bit RISC CPU Design & FPGA Implementation
- DescriptionDesigned and implemented a complete 16-bit RISC processor in VHDL, integrating datapath, control unit, and memory to execute a custom instruction set. The project progressed from fundamental components (register file, ALU, memory) to full CPU integration, with verification through Quartus simulation, waveform analysis, and FPGA deployment. The final system supports arithmetic, logical, shift/rotate, immediate, and branch operations using MIF-initialized instruction and data memory.
- RoleDefined the instruction set architecture and corresponding micro-operations, and developed all major VHDL modules including the ALU, register file, program counter, memory, and control unit. Implemented the control logic as a finite state machine and integrated the complete datapath into a working processor. Created testbenches to validate functionality and performed detailed waveform and timing analysis in Quartus, culminating in a formal technical report and presentation.
- ImpactThis project demonstrates the ability to design a processor end-to-end, from architectural definition to hardware implementation and verification. It reinforces a strong understanding of digital system design, timing, and control flow, and showcases the capability to translate theoretical computer architecture concepts into a fully functional CPU on FPGA hardware.
Description
Toronto Metropolitan University
January 2025
Designed and implemented a 16-bit RISC CPU in VHDL on FPGA, including ISA definition, datapath, control unit, and memory integration. Verified functionality using Quartus simulations, waveform analysis, and hardware testing.