{"id":99,"date":"2020-06-11T12:06:30","date_gmt":"2020-06-11T12:06:30","guid":{"rendered":"http:\/\/danielavellaordonez.com\/?post_type=fw-portfolio&#038;p=99"},"modified":"2026-03-30T14:15:02","modified_gmt":"2026-03-30T14:15:02","slug":"cpu-project","status":"publish","type":"fw-portfolio","link":"https:\/\/danielavellaordonez.com\/fr\/project\/cpu-project\/","title":{"rendered":"16-bit RISC CPU Design &amp; FPGA Implementation"},"content":{"rendered":"<div data-elementor-type=\"wp-post\" data-elementor-id=\"99\" class=\"elementor elementor-99\">\n\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-0695f0d elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"0695f0d\" data-element_type=\"section\" data-e-type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-65eb4fa\" data-id=\"65eb4fa\" data-element_type=\"column\" data-e-type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-bbb7094 animated-slow elementor-invisible elementor-widget elementor-widget-image\" data-id=\"bbb7094\" data-element_type=\"widget\" data-e-type=\"widget\" data-settings=\"{&quot;_animation&quot;:&quot;fadeInDown&quot;}\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<img fetchpriority=\"high\" decoding=\"async\" width=\"1024\" height=\"768\" src=\"https:\/\/danielavellaordonez.com\/wp-content\/uploads\/2020\/06\/olivier-collet-JMwCe3w7qKk-unsplash-1024x768.jpg\" class=\"attachment-large size-large wp-image-321\" alt=\"\" srcset=\"https:\/\/danielavellaordonez.com\/wp-content\/uploads\/2020\/06\/olivier-collet-JMwCe3w7qKk-unsplash-1024x768.jpg 1024w, https:\/\/danielavellaordonez.com\/wp-content\/uploads\/2020\/06\/olivier-collet-JMwCe3w7qKk-unsplash-scaled-600x450.jpg 600w, https:\/\/danielavellaordonez.com\/wp-content\/uploads\/2020\/06\/olivier-collet-JMwCe3w7qKk-unsplash-300x225.jpg 300w, https:\/\/danielavellaordonez.com\/wp-content\/uploads\/2020\/06\/olivier-collet-JMwCe3w7qKk-unsplash-768x576.jpg 768w, https:\/\/danielavellaordonez.com\/wp-content\/uploads\/2020\/06\/olivier-collet-JMwCe3w7qKk-unsplash-1536x1152.jpg 1536w, https:\/\/danielavellaordonez.com\/wp-content\/uploads\/2020\/06\/olivier-collet-JMwCe3w7qKk-unsplash-2048x1536.jpg 2048w, https:\/\/danielavellaordonez.com\/wp-content\/uploads\/2020\/06\/olivier-collet-JMwCe3w7qKk-unsplash-16x12.jpg 16w\" sizes=\"(max-width: 1024px) 100vw, 1024px\" \/>\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-66d31df elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"66d31df\" data-element_type=\"section\" data-e-type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-22a99b4\" data-id=\"22a99b4\" data-element_type=\"column\" data-e-type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-02b1933 elementor-widget elementor-widget-breezycv-info-list\" data-id=\"02b1933\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"breezycv-info-list.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div class=\"info-list\"><ul><li><span class=\"title\">Description<\/span><span class=\"value\">Designed and implemented a complete 16-bit RISC processor in VHDL, integrating datapath, control unit, and memory to execute a custom instruction set. The project progressed from fundamental components (register file, ALU, memory) to full CPU integration, with verification through Quartus simulation, waveform analysis, and FPGA deployment. The final system supports arithmetic, logical, shift\/rotate, immediate, and branch operations using MIF-initialized instruction and data memory.<\/span><\/li><li><span class=\"title\">Role<\/span><span class=\"value\">Defined the instruction set architecture and corresponding micro-operations, and developed all major VHDL modules including the ALU, register file, program counter, memory, and control unit. Implemented the control logic as a finite state machine and integrated the complete datapath into a working processor. Created testbenches to validate functionality and performed detailed waveform and timing analysis in Quartus, culminating in a formal technical report and presentation.<\/span><\/li><li><span class=\"title\">Impact<\/span><span class=\"value\">This project demonstrates the ability to design a processor end-to-end, from architectural definition to hardware implementation and verification. It reinforces a strong understanding of digital system design, timing, and control flow, and showcases the capability to translate theoretical computer architecture concepts into a fully functional CPU on FPGA hardware.<\/span><\/li><\/ul><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<\/div>","protected":false},"featured_media":317,"template":"","fw-portfolio-category":[6],"class_list":["post-99","fw-portfolio","type-fw-portfolio","status-publish","has-post-thumbnail","hentry","fw-portfolio-category-detailed"],"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/danielavellaordonez.com\/fr\/wp-json\/wp\/v2\/fw-portfolio\/99","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/danielavellaordonez.com\/fr\/wp-json\/wp\/v2\/fw-portfolio"}],"about":[{"href":"https:\/\/danielavellaordonez.com\/fr\/wp-json\/wp\/v2\/types\/fw-portfolio"}],"version-history":[{"count":15,"href":"https:\/\/danielavellaordonez.com\/fr\/wp-json\/wp\/v2\/fw-portfolio\/99\/revisions"}],"predecessor-version":[{"id":456,"href":"https:\/\/danielavellaordonez.com\/fr\/wp-json\/wp\/v2\/fw-portfolio\/99\/revisions\/456"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/danielavellaordonez.com\/fr\/wp-json\/wp\/v2\/media\/317"}],"wp:attachment":[{"href":"https:\/\/danielavellaordonez.com\/fr\/wp-json\/wp\/v2\/media?parent=99"}],"wp:term":[{"taxonomy":"fw-portfolio-category","embeddable":true,"href":"https:\/\/danielavellaordonez.com\/fr\/wp-json\/wp\/v2\/fw-portfolio-category?post=99"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}