BJJ — No-Gi Bronze (Great Lakes Open)
Aug 2025. Builds composure under pressure, fast adaptation, and accountability — useful under delivery deadlines.
View medal
Personal Website
Daniel Avella Ordonez
I'm a Computer Engineering student at Toronto Metropolitan University, currently completing a 16-month co-op at the Independent Electricity System Operator (IESO).
I'm passionate about developing innovative systems, merging technical precision with real-world applications to create meaningful impact.
About me
I'm a Computer Engineering student at Toronto Metropolitan University with a passion for technology, design, and innovation. My journey blends technical skill with creativity, shaped by hands-on experience during a 16-month co-op at the Independent Electricity System Operator (IESO).
I find inspiration in the challenge of solving real-world problems—whether through code, engineering design, or personal growth. My life outside of work includes intense MMA training, strength workouts, and a deep commitment to becoming the most capable version of myself—mentally and physically.
If you're curious to follow my work, thoughts, or training journey, you can connect with me below:
Work Experience
Process Engineering Analyst (Co-op)
IESO
May 2025 – Present
Process automation & analytics for Ontario’s electricity market operations.
Built PI System tooling and SCADA validation routines to improve telemetry quality; standardized tag mapping and change tracking.
Authored stakeholder runbooks and shipped Azure DevOps pipelines for reproducible analyses and traceable releases.
Visit IESO
Web Architect & Tech Consultant
Fila’s General Construction
Oct 2023 – May 2025
Launched the company website and Google Business Profile.
Implemented local SEO, analytics, and lead capture/CRM; ran targeted local ads and Google ads with conversion tracking.
Visit site
Customer Wellness Associate
Healthy Planet
2024 – Present
Supported wellness product education, POS, and inventory.
Produce Clerk
Marilu’s Market
2021 – 2022
Managed produce displays and freshness, supported customers.
Education
Bachelor of Engineering in Computer Engineering
Toronto Metropolitan University
2020 – 2025 (Expected)
Cumulative GPA: 3.4
Bouck & Hague Memorial Award
TMU Student Awards & Scholarships
2025
Academic excellence & community involvement
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Dean’s List Recipient
TMU Engineering Faculty
Winter 2025
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Dean’s List Recipient
TMU Engineering Faculty
2022 – 2023
Download PDF
IEEE CSTMC Certificate
Software Fundamentals Series
Dec 2022
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Certifications & Licenses
Ontario Security Guard Course Completion
CRJMC Verified
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Standard First Aid & CPR/AED Level C (Blended)
Certified: 2025 (CSA Z1210-17)
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Licensed Ontario Security Guard
Valid through May 2027
Hospital Volunteer
Joseph Brant Hospital — 200+ hours (2017–2019)
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Skills
A focused snapshot of what I bring to engineering teams.
Engineering
Python C/C++ JavaScript Web Tech
Systems & Data
System Architecture Data Pipelines Excel Pandas Plotly
DevOps & Practices
Git Docker Kubernetes CI/CD Secure Coding
Documentation Collaboration Self-Discipline Adaptability
Show applied examples
Market Analysis Tools
Python + Pandas pipelines, SCADA validation, and DevOps releases for reproducible analyses.
SMB Web Launch
Astro site, SEO/analytics, CRM capture, and local ad ops with conversion tracking.
Secure Coding
Input validation, dependency scanning, least-privilege patterns, and docs for teammates.
Portfolio
Selected work
Brief, high-impact snapshots from industry and academia—where systems thinking meets clean UX. Deeper dives soon.
IESO — Independent Electricity System Operator
Market analytics toolkit for Ontario’s grid telemetry: reproducible signal pipelines, automated oscillation scoring, and observability dashboards.
Project 1: IESO market analytics toolkit
Visit projectDescription:
Built a frequency-domain analysis flow (FFT/PSD) over rolling windows to characterize normal oscillations (0.01–15 Hz), standardize tag mapping, and surface band maxima for thresholding. Integrated PI System / SCADA ingestion and shipped pipelines via Azure DevOps with runbooks and dashboards.
Role:
Signal processing · PI/SCADA integration · DevOps automation · telemetry QA · stakeholder documentation.
Impact:
Cleaner telemetry, faster diagnostics, and clearer operator visibility into oscillatory behavior across assets.
COE608 — Computer Organization & Architecture
Toronto Metropolitan University · B.Eng. Computer Engineering · RISC CPU (VHDL on FPGA). Computer Organization & Architecture. Designed and verified a 16-bit RISC processor end-to-end: ISA, datapath, control, memory, and timing.
Project 4: COE608 — Complete CPU
Computer Organization & Architecture · RISC datapath + control · FPGA/Quartus
View report (PDF)Description:
Course labs progressed from PC/register file and bus interconnects → a 32-bit ALU (simulation + board) → data memory → full datapath → control-unit FSM → final CPU integration. The completed core executes a small instruction set (e.g., ADD/SUB, AND/OR, shifts/rotates, immediate loads, and conditional branches) with MIF-backed instruction/data memory and Quartus timing/waveform validation.
Role:
Defined ISA semantics and micro-ops; authored VHDL for PC, register file, ALU, memory, and control FSM; integrated top level; created testbenches and waveform checks; delivered IEEE-style report and oral demo.
COE692 — Software Design & Architecture
B.Eng. Computer Engineering at Toronto Metropolitan University (TMU). Men’s online clothing store (Java EE, microservices. Multi-service flow (Login, Products, Cart, Frontend) originally on Tomcat/Docker/K8s with JWT & KubeMQ; mirrored to static for a smooth, zero-server demo.
Description:
Service-oriented JSP/Servlets with clear boundaries (auth, catalog, cart, UI), reproducible packaging, and ops runbooks. The static mirror preserves UX while removing runtime dependencies.
Role:
Service design • JSP/Servlets • JWT auth • inter-service integration • Docker/K8s manifests • UX flows • documentation.
ELE404 — Electronic Circuits I
B.Eng. Computer Engineering, Toronto Metropolitan University (TMU). Single-supply, multistage BJT amplifier: biasing, small-signal model, and gain/bandwidth/swing targets; validated in Multisim with sweeps and corner checks.
Project 4: BJT amplifier — design & validation
View report (PDF)Description:
DC bias design, small-signal analysis, load-line & stability margins; cascaded stages with current sources/mirrors; impedance targets; verification against spec with structured measurements.
Deliverables:
Schematics, hand calculations, Multisim parametric sweeps, corner validation, and a formal design report with results and discussion.
Personal
Interests & Personal Achievements
Competition, strategy, endurance, and consistency — the same habits I bring to engineering work.
Chess — Silver medal
Long-horizon planning and pattern recognition — the same muscles used in systems design and trade-offs.
Endurance — Sleeping Giant summit
Pacing and grit over long climbs. Mirrors how I approach large projects: chunking, recovery, steady velocity.
View photoCalisthenics — first muscle-up
Five months of steady progress. Reinforced habit design, progressive overload, and patient iteration — just like engineering.
View videoScience & Technology Award (Middle school)
Recognized for top performance across science/technology — early proof that disciplined practice compounds.
View image
